1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a nonvolatile semiconductor memory device.
2. Description of the Related Art
Interference has increased between adjacent cells along with miniaturization of a nonvolatile semiconductor memory device, necessitating reduction in the thickness of an ONO film (including oxide, nitride and oxide films) applied as an interelectrode insulating film in consequence.
When high electric-field stress is applied to the ONO film as the interelectrode insulating film to carry out writing or erasing, electron trapping occurs in the nitride film of the ONO film. There is a characteristic that an increase in own electric field of the nitride film caused by the electron trapping results in a reduction of an electric field applied to the ONO film, thereby improving leakage characteristics.
Reducing the thickness of the ONO film is difficult when it is carried out by reducing the thickness of the oxide film to provide device reliability. Thus, the ONO film is made thinner by reducing the thickness of the nitride film. However, making the nitride film thinner reduces the number of trapped electrons, and provides unsatisfactory electric field reduction, causing a problem of increased leakage current.
Jpn. Pat. Appln. KOKAI Publication No. 11-261038 discloses a configuration of a memory transistor which includes a semiconductor substrate having a channel forming region, an isolation insulating film buried in a trench formed in the semiconductor substrate to isolate the channel forming region, a tunnel insulating film formed on the channel forming region, a floating gate formed on the tunnel insulating film and having at least two opposed ends formed higher than a part between the ends, an intermediate insulating film formed to cover the entire surface of the floating gate, a control gate formed on the intermediate insulating film, and a source/drain region formed to be connected with the channel forming region.
Jpn. Pat. Appln. KOKAI Publication No. 11-103033 discloses a method which includes forming a pad section for a floating gate electrode by patterning a CVDSiO2 film/polysilicon film, forming a trench in a semiconductor substrate surface by using the floating gate electrode pad having HTO and Si3N4 films deposited therein as a mask, and forming a thick thermal oxide film by thermal oxidation so that an interface position between the oxide film on the trench and the semiconductor substrate can be on a channel center side more than the end of the floating gate electrode pad.
Jpn. Pat. Appln. KOKAI Publication No. 9-64205 discloses a method which includes forming a silicon nitride film, and then adding silicon (Si), nitrogen (N) or oxygen (O) to the silicon nitride film.